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Este ejemplo muestra el Convertidor ADC (Analógico a Digital) Sigma Delte de Segundo Orden que a diferencia del Convertidor de primer orden, tiene dos etapas integradoras de las señales de diferencia que provienen de los sumadores. En este caso, a la salida del segundo integrador aparece el comparador como convertidor ADC de 1 bit cuya salida alimenta al bloque convertidor DAC (Digital a Analógico) de 1 bit y a la etapa de Filtro Digital o Diezmador.
La teoría, en idioma inglés, de este diseño se encuentra en el documento "How delta-sigma ADCs work, Part 1", publicado por la empresa Texas Instruments de Bonnie Baker, disponible en el enlace https://www.ti.com/lit/pdf/slyt423?keyMatch=BONNIE%20BAKER&tisearch=Search-EN-technicaldocument
Copyright 2009 Ivan Griffin
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Este gráfico presenta las comparaciones de la compansión de una señal telefónica de entrada cuando es comprimida usando la Ley-A y la Ley-Mu tal se describen en la Recomendación G.711 de la Unión Internacional de Telecomunicaciones.
De la gráfica se deduce que la compansión con ambas leyes no presenta mayores diferencias.